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1 data sheet acquired from harris semiconductor schs191c features buffered inputs asynchronous parallel load fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c597 and cd74hct597 are high-speed silicon gate cmos devices that are pin-compatible with the lsttl 597 devices. each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. each register is controlled by its own clock. a ?ow on the parallel load input ( pl) shifts parallel stored data asynchronously into the shift register. a ?ow master input ( mr) clears the shift register. serial input data can also be synchronously shifted through the shift register when pl is high. pinout cd54hc597 (cerdip) cd74hc597 (pdip, soic, sop) cd74hct597 (pdip, soic) top view ordering information part number temp. range ( o c) package cd54hc597f3a -55 to 125 16 ld cerdip cd74hc597e -55 to 125 16 ld pdip cd74hc597m -55 to 125 16 ld soic cd74hc597mt -55 to 125 16 ld soic cd74hc597m96 -55 to 125 16 ld soic cd74hc597nsr -55 to 125 16 ld sop cd74hct597e -55 to 125 16 ld pdip cd74hct597m -55 to 125 16 ld soic cd74hct597mt -55 to 125 16 ld soic cd74hct597m96 -55 to 125 16 ld soic note: when ordering, use the entire part number. the suf?es 96 and r denote tape and reel. the suf? t denotes a small-quantity reel of 250. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 d1 d2 d3 d4 d5 d6 gnd d7 v cc d s pl st cp sh cp mr q7 d0 january 1998 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc597, cd74hc597, cd74hct597 high-speed cmos logic 8-bit shift register with input storage [ /title ( cd74 h c597 , c d74 h ct59 7 ) / sub- j ect ( high s peed c mos
2 functional diagram 9 1 2 3 4 6 12 7 5 d1 d2 d3 d4 d5 d6 d7 st cp q7 11 13 10 15 14 d0 ds sh cp pl mr 8 f/f storage reg. 8-bit shift reg. parallel data inputs function table st cp sh cp pl mr function x x x data loaded to input flip-flops x l h data loaded from inputs to shift register no clock edge x l h data transferred from input flip-flops to shift register x x l l invalid logic, state of shift register indeterminate when signals removed x x h l shift register cleared x h h shift register clocked qn = qn-1, q0 = d s h = high voltage level, l = low voltage level, x = don? care, = transition from low to high cp level cd54hc597, cd74hc597, cd74hct597
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 1) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 ns (sop) package . . . . . . . . . . . . . . . . . . . . . . . . . 64 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a cd54hc597, cd74hc597, cd74hct597
4 quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 a additional quiescent device current per input pin: 1 unit load ? i cc (note 2) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 2. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. hct input loading table input unit loads d s 0.2 d n 0.3 pl, mr 1.5 st cp , sh cp 1.5 note: unit load is ? i cc limit specified in dc electrical specifications table, e.g., 360 a max. at 25 o c. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max prerequisite for switching speci?ations parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max hc types sh cp frequency f max 2 6 - - 5 - - 4 - - mhz 4.5 30 - - 25 - - 20 - - mhz 6 35 - - 29 - - 23 - - mhz cd54hc597, cd74hc597, cd74hct597
5 sh cp pulse width t w 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 614- -17- -20- -ns st cp pulse width t w 260- -75- -90- -ns 4.5 12 - - 15 - - 18 - - ns 610- -13- -15- -ns mr pulse width t w 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 614- -17- -20- -ns pl pulse width t w 2 70 - - 90 - - 105 - - ns 4.5 14 - - 18 - - 21 - - ns 612- -15- -18- -ns st cp to sh cp setup time t su 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 617- -21- -26- -ns d s to sh cp setup time d n to st cp setup time t su 250- -65- -75- -ns 4.5 10 - - 13 - - 15 - - ns 6 9 - - 11 - - 13 - - ns st cp to sh cp setup time t h 20--0- -0--ns 4.5 0 - - 0 - - 0 - - ns 60--0- -0--ns d s to sh cp hold time d n to st cp hold time t h 23--3- -3--ns 4.5 3 - - 3 - - 3 - - ns 63--3- -3--ns mr to sh cp removal time t rem 23--3- -3--ns 4.5 3 - - 3 - - 3 - - ns 63--3- -3--ns hct types sh cp frequency f max 4.5 25 - - 20 - - 16 - - mhz sh cp pulse width t w 4.5 20 - - 25 - - 30 - - ns st cp pulse width t w 4.5 13 - - 16 - - 20 - - ns mr pulse width t w 4.5 18 - - 23 - - 27 - - ns pl pulse width t w 4.5 16 - - 20 - - 24 - - ns st cp to sh cp setup time t su 4.5 24 - - 30 - - 36 - - ns prerequisite for switching speci?ations (continued) parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max cd54hc597, cd74hc597, cd74hct597
6 d s to sh cp setup time d n to st cp setup time t h 4.5 10 - - 13 - - 15 - - ns st cp to sh cp hold time t h 4.5 0 - - 0 - - 0 - - ns d s to sh cp hold time d n to st cp hold time t h 4.5 3 - - 3 - - 3 - - ns mr to sh cp removal time t rem 4.5 10 - - 13 - - 15 - - ns switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o cto85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay t plh, t phl c l = 50pf 2 - - 175 - 220 - 265 ns sh cp to q7 4.5 - - 35 - 44 - 53 ns c l =15pf 5 - 14 - - - - - ns c l = 50pf 6 - - 30 - 37 - 45 ns pl to q7 t plh, t phl c l = 50pf 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns c l =15pf 5 - 17 - - - - - ns c l = 50pf 6 - - 34 - 43 - 51 ns st cp to q7 t plh, t phl c l = 50pf 2 - - 240 - 300 - 360 ns 4.5 - - 48 - 60 - 72 ns c l =15pf 5 - 20 - - - - - ns c l = 50pf 6 - - 41 - 51 - 61 ns mr to q7 t plh, t phl c l = 50pf 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns c l =15pf 5 - 14 - - - - - ns c l = 50pf 6 - - 30 - 37 - 45 ns output transition time t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c i c l = 50pf - - - 10 - 10 - 10 pf power dissipation capacitance, (notes 3, 4) c pd - 5 - 13.5 - - - - - pf hct propagation delay t plh, t phl sh cp to q7 c l = 50pf 4.5 - - 38 - 48 - 57 ns c l = 15pf 5 - 16 - - - - - ns pl to q7 t plh, t phl c l = 50pf 4.5 - - 48 60 72 ns c l = 15pf 5 - 20 - - - - - ns st cp to q7 t plh, t phl c l = 50pf 4.5 - - 56 70 84 ns c l = 15pf 5 - 23 - - - - - ns prerequisite for switching speci?ations (continued) parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max cd54hc597, cd74hc597, cd74hct597
7 mr to q7 t plh, t phl c l = 50pf 4.5 - - 44 - 55 - 66 ns c l = 15pf 5 - 18 - - - - - ns output transition time t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i c l = 50pf - - - 10 - 10 - 10 pf power dissipation capacitance, (notes 3, 4) c pd - 5 - 18.5 - - - - - pf notes: 3. c pd is used to determine the dynamic power consumption, per package. 4. p d =c pd v cc 2 f i + (c l v cc 2 f o ) where: f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o cto85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width figure 3. hc transition times and propagation delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd54hc597, cd74hc597, cd74hct597
8 figure 5. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 6. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits test circuits and waveforms (continued) t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54hc597, cd74hc597, cd74hct597
9 timing diagram shift clock sh cp serial date d s master reset mr parallel load pl storage clock st cp d0 d1 d2 d3 d4 d5 d6 d7 q7 parallel data inputs reset shift register serial shift l h h h h h hhhh h h h hh l l ll l l l l lll l l l l l l l l h l l l l h h l h load flip-flops load flip-flops parallel load shift register parallel load shift register parallel load flip-flop s and shift register serial shift serial shift serial shift cd54hc597, cd74hc597, cd74hct597
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 5962-8681701ea active cdip j 16 1 tbd a42 n / a for pkg type -55 to 125 5962-8681701ea cd54hc597f3a cd54hc597f3a active cdip j 16 1 tbd a42 n / a for pkg type -55 to 125 5962-8681701ea cd54hc597f3a cd74hc597e active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hc597e cd74hc597ee4 active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hc597e cd74hc597m active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hc597m96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hc597m96e4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hc597m96g4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hc597mg4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hc597mt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hc597nsr active so ns 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc597m cd74hct597e active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hct597e cd74hct597m active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hct597m cd74hct597m96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hct597m cd74hct597m96g4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hct597m cd74hct597mg4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hct597m cd74hct597mt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hct597m
package option addendum www.ti.com 10-jun-2014 addendum-page 2 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of cd54hc597, cd74hc597 : ? catalog: cd74hc597 ? military: cd54hc597
package option addendum www.ti.com 10-jun-2014 addendum-page 3 note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cd74hc597m96 soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 cd74hc597nsr so ns 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 q1 cd74hct597m96 soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) cd74hc597m96 soic d 16 2500 333.2 345.9 28.6 cd74hc597nsr so ns 16 2000 367.0 367.0 38.0 cd74hct597m96 soic d 16 2500 333.2 345.9 28.6 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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